This invention relates generally to high-power electrical devices, and more particularly the invention relates to voltage limiting and electrostatic discharge protection in a semiconductor power device.
Power semiconductor devices such as MESFETs or bipolar transistors which operate at high frequencies typically are connected to capacitive devices such as discrete MOSCAPs for input frequency and impedance matching. The discrete MOSCAP devices are mounted in a semiconductor package along with the semiconductor transistor chip and are interconnected therewith by suitable means such as wire bonding.
The power device must be protected against an input voltage overload which could damage or destroy the device. Heretofore, a voltage limiting or electrostatic discharge device (ESD) such as a zener diode, avalanche diode, or transistor has been integrated into the power transistor chip or power integrated circuit chip. While this integration of components on the power chip is readily accomplished in the fabrication process, use of the power chip for the ESD device is costly in loss of power chip space. Further, size and flexibility of the electrostatic discharge device along with ability to test the electrostatic discharge device and/or the transistor separately are compromised.
The present invention is directed to overcoming these limitations in prior art power device structures.
In accordance with the invention, a power transistor device for high frequency applications includes a power transistor in a first discrete semiconductor chip, a capacitor and a voltage limiting device in a second discrete semiconductor chip, and a package for receiving and sealing the first and second semiconductor chips. Electrical connectors connect the capacitor and voltage limiting device in the second chip to the power transistor in the first chip.
In preferred embodiments of the invention, the voltage limiting device comprises a diode or transistor and the capacitor is a MOSCAP which are connected in parallel. Since the MOSCAP chip has ample space for fabricating the voltage limiting or ESD device, increased space is available in the semiconductor chip for the power transistor thus allowing greater flexibility in the power device fabrication.
The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawing.